(1) Field of the Invention
The present invention relates to methods for fabricating electronic devices and especially to methods for fabricating electronic devices capable of controlling threshold voltages of transistors having drain extension structures with stability.
(2) Description of the Related Art
To enhance the function of electronic devices such as semiconductor integrated circuit devices, it has become essential to improve the performances of semiconductor devices forming the electronic devices. To achieve this, for MOS transistors that are often used as semiconductor elements at present, the size of gate electrodes has been reduced and semiconductor elements having gate-electrode sizes smaller than 100 nm are being manufactured.
To reduce the gate-electrode sizes to such a degree, techniques for processing gate electrodes have progressed rapidly. For example, lithography for transferring a pattern to a substrate allows the gate-electrode size to be controlled to 90 nm or less using an ArF excimer laser. In addition, the processing accuracy in dry etching for actually forming gate electrodes has been increasing.
However, these processing techniques utilize limitations of their associated physical phenomena, so that control of these phenomena has become more and more difficult. Accordingly, in mass production of devices, variations among devices, lots and, to the worst, wafers occur, and the variation range in characteristics of semiconductor elements depending on the accuracy in processing gate electrodes are disadvantageously the same as the range of specifications of non-defective products under current circumstances.
To correct such variations, feedback techniques in which results of performance inspection performed on elements before shipment of products are reflected in conditions for fabricating the products and feedforward techniques in which variations in performance of final elements are predicted from variations in a given fabrication process step of a product and results of this prediction are reflected in fabrication conditions in a subsequent process step have been proposed to date (see, for example, Japanese Unexamined Patent Publication No. 58-197878).
Specifically, a conventional feedforward technique is performed in the following manner. After a gate electrode has been formed through lighography and etching, the size of this gate electrode is measured. Then, the measured size of the gate electrode is compared with a predetermined reference value so as to obtain a deviation from an intended size of the gate electrode. Thereafter, the obtained deviation is applied to a database so that conditions of annealing for activating source/drain (S/D) are modified. This allows characteristics of element performance to be corrected. Subsequently, a wiring process is performed.
In this conventional technique, if a deviation of the gate-electrode size is detected, a feedforward process of, for example, modifying the annealing temperature for activating source/drain from a standard condition is performed such that an electrical and effective gate length Leff is equal to a length Leff obtained when the gate-electrode size has a design value.